FazyRV -- A Scalable RISC-V Core
FazyRV is a minimal-area RISC-V RV32 core featuring a scalable data path that can be configured to 1, 2, 4, or 8 bits at synthesis time. It is designed for resource-constrained FPGA architectures like iCE40 and ECP5, offering fine-tuned trade-offs between hardware area and performance while maintaining compatibility with the LiteX SoC builder.